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ISL84051, ISL84052, ISL84053
Data Sheet March 15, 2007 FN6047.7
Low Voltage, Single and Dual Supply, 8 to 1 Multiplexer, Dual 4 to 1 Multiplexer and a Triple SPDT Analog Switch
The Intersil ISL84051, ISL84052, ISL84053 devices are precision, bidirectional, analog switches configured as a 8-Channel multiplexer/demultiplexer (ISL84051), a dual differential 4-Channel multiplexer/demultiplexer (ISL84052) and a triple single pole/double throw (SPDT) switch (ISL84053) designed to operate from a single +2V to +12V supply or from a 2V to 6V supply. All devices have an inhibit pin to simultaneously open all signal paths. ON resistance is 60 with a 5V supply and 125 with a single +5V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 0.1nA at +25C or 5nA at +85C with a 5V supply. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS logic compatibility when using a single +3.3V and +5V supply or dual 5V supplies. The ISL84051 is a 8 to 1 multiplexer device. The ISL84052 is a dual 4 to 1 multiplexer device. The ISL84053 is a committed triple SPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE ISL84051 CONFIGURATION 5V rON 5V tON/tOFF 5V rON 5V tON/tOFF 3V rON 3V tON/tOFF Packages 8:1 Mux 60 50ns/40ns 125 90ns/60ns 250 180ns/100ns ISL84052 DUAL 4:1 Mux 60 50ns/40ns 125 90ns/60ns 250 180ns/100ns ISL84053 TRIPLE SPDT 60 50ns/40ns 125 90ns/60ns 250 180ns/100ns 16 Ld SOIC, 16 Ld SSOP
Features
* Drop-in Replacements for MAX4051/A, MAX4052/A and MAX4053/A * Pin Compatible with MAX4581, MAX4582, MAX4583 and with Industry Standard 74HC4051, 74HC4052 and 74HC4053 * ON Resistance (rON) Max, VS = 5V . . . . . . . . . . . . 100 * ON Resistance (rON) Max, VS = +3V . . . . . . . . . . . . 525 * rON Matching Between Channels . . . . . . . . . . . . . . . . . . <6 * Low Charge Injection . . . . . . . . . . . . . . . . . . . . . 10pC (Max) * Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V * Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . . 2V to 6 * Fast Switching Action (VS = +5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns * Guaranteed Max Off-leakage @ VS = 5V . . . . . . . . . . 5nA * Guaranteed Break-Before-Make * TTL, CMOS Compatible * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Portable Equipment * Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems * Test Equipment - Medical Ultrasound - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE - Electrocardiograph * Audio and Video Signal Routing * Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits
16 Ld SOIC, 16 Ld SOIC, 16 Ld SSOP 16 Ld SSOP 16 Ld TSSOP 16 Ld TSSOP
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003-2004, 2006-2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL84051, ISL84052, ISL84053 Pinouts
ISL84051 (16 LD SOIC, SSOP, TSSOP) TOP VIEW
NO1 1 NO3 2 COM 3 NO7 4 NO5 5 INH 6 V- 7 GND 8 LOGIC 16 V+ 15 NO2 14 NO4 13 NO0 12 NO6 11 ADDC 10 ADDB 9 ADDA
ISL84052 (16 LD SOIC, SSOP, TSSOP) TOP VIEW
NO0B 1 NO1B 2 COMB 3 NO3B 4 NO2B 5 INH 6 V- 7 GND 8 LOGIC 16 V+ 15 NO1A 14 NO2A 13 COMA 12 NO0A 11 NO3A 10 ADDB 9 ADDA
ISL84053 (16 LD SOIC, SSOP) TOP VIEW
NOB 1 NCB 2 NOA 3 COMA 4 NCA 5 INH 6 V- 7 GND 8 16 V+ 15 COMB 14 COMC 13 NOC 12 NCC 11 ADDC 10 ADDB 9 ADDA
NOTE: 1. Switches Shown for Logic "0" Inputs.
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Ordering Information
PART NUMBER ISL84051IB* PART MARKING 84051IB TEMP. RANGE (C) PACKAGE PKG. DWG. # M16.15 M16.15 M16.15A M16.15A
Truth Tables
ISL84051 INH 1 0 0 0 0 0 0 0 0 ADDC X 0 0 0 0 1 1 1 1 ADDB X 0 0 1 1 0 0 1 1 ADDA X 0 1 0 1 0 1 0 1 SWITCH ON None NO0 NO1 NO2 NO3 NO4 NO5 NO6 NO7
-40 to +85 16 Ld SOIC -40 to +85 16 Ld SOIC (Pb-free) -40 to +85 16 Ld SSOP -40 to +85 16 Ld SSOP (Pb-free)
ISL84051IBZ* 84051IBZ (Note) ISL84051IA* 84051 IA
ISL84051IAZ* 84051 IAZ (Note) ISL84051IVZ* 84051 IVZ (Note) ISL84052IB* 84052IB
-40 to +85 16 Ld TSSOP M16.173 (Pb-free) -40 to +85 16 Ld SOIC -40 to +85 16 Ld SOIC (Pb-free) -40 to +85 16 Ld SSOP -40 to +85 16 Ld SSOP (Pb-free) M16.15 M16.15 M16.15A M16.15A
ISL84052IBZ* 84052IBZ (Note) ISL84052IA* 84052 IA
ISL84052IAZ* 84052 IAZ (Note) ISL84052IVZ* 84052IVZ (Note) ISL84053IB* 84053IB
-40 to +85 16 Ld TSSOP M16.173 (Pb-free) -40 to +85 16 Ld SOIC -40 to +85 16 Ld SOIC (Pb-free) -40 to +85 16 Ld SSOP -40 to +85 16 Ld SSOP (Pb-free) M16.15 M16.15
ISL84052 INH 1 0 ADDB X 0 0 1 1 ADDA X 0 1 0 1 SWITCH ON None NO0 NO1 NO2 NO3
ISL84053IBZ* 84053IBZ (Note) ISL84053IA* 84053 IA
M16.15A M16.15A
0 0 0
ISL84053IAZ* 84053 IAZ (Note)
*Add "-T" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL84053 INH 1 0 ADDC X X X X X 0 1 ADDB X X X 0 1 X X ADDA X 0 1 X X X X SWITCH ON None NCA NOA NCB NOB NCC NOC
Pin Description
PIN V+ VGND INH COM NO NC ADD FUNCTION Positive Power Supply Input Negative Power Supply Input. Connect to GND for Single Supply Configurations. Ground Connection Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin Address Input Pin
0 0 0 0 0
NOTE: Logic "0" 0.8V. Logic "1" 2.4V, with V+ between 2.7V and 10V. X = Don't Care.
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053
Absolute Maximum Ratings
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 0.3V Input Voltages INH, NO, NC, ADD (Note 2) . . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 100mA ESD Rating HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >2kV
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 115 16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 160 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C (Lead Tips Only)
Operating Conditions
Temperature Range ISL8405XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, rON
Full VS = 5V, ICOM = 1mA, VNO or VNC = 3V, (See Figure 5) VS = 5V, ICOM = 1mA, VNO or VNC = 3V, (Note 6) +25 Full +25 Full VS = 5V, ICOM = 1mA, VNO or VNC = 3V, 0V, (Note 7) VS = 5.5V, VCOM = 4.5V, VNO or VNC = 4.5V, (Note 8) VS = 5.5V, VCOM = 4.5V, VNO or VNC = 4.5V, (Note 8) VS = 5.5V, VCOM = 4.5V, VNO or VNC = 4.5V, (Note 8) VS = 5.5V, VCOM = VNO or VNC = 4.5V, (Note 8) VS = 5.5V, VCOM = VNO or VNC = 4.5V, (Note 8) +25 Full +25 Full +25 Full +25 Full +25 Full +25 Full
V-0.1 -5 -0.1 -5 -0.1 -2.5 -0.1 -5 -0.1 -2.5
60 0.002 0.002 0.002 0.002 0.002 -
V+ 100 125 6 12 10 15 0.1 5 0.1 5 0.1 2.5 0.1 5 0.1 2.5
V nA nA nA nA nA nA nA nA nA nA
rON Matching Between Channels, rON rON Flatness, rFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF), (ISL84051) COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) COM ON Leakage Current, ICOM(ON), (ISL84051) COM ON Leakage Current, ICOM(ON), (ISL84052, ISL84053) DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL
Full Full VS = 5.5V, VINH, VADD = 0V or V+ Full
2.4 -1
0.03
0.8 1
V V A
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053
Electrical Specifications - 5V Supply
Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (C) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS
PARAMETER DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON
VS = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) VS = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) VS = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3, (See Figure 1) VS = 5.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) ISL84051 ISL84052 ISL84053
+25 Full +25 Full +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25 +25
2 -
50 40 75 10 2 3 21 12 9 26 18 14 <90 < -90
175 225 150 200 250 10 -
ns ns ns ns ns ns pC pF pF pF pF pF pF pF dB dB
Inhibit Turn-OFF Time, tOFF
Address Transition Time, tTRANS Break-Before-Make Time, tBBM Charge Injection, Q NO/NC OFF Capacitance, COFF COM OFF Capacitance, COFF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
ISL84051 ISL84052 ISL84053
OFF Isolation Crosstalk, (Note 9) (ISL84052, ISL84053 Only)
RL = 50, CL = 15pF, f = 100kHz, VNO or VNC = 1VRMS, (See Figures 4 and 6)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ VS = 5.5V, VINH, VADD = 0V or V+, Switch On or Off Full +25 Full 25 Full NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. rON = rON (MAX) - rON (MIN). 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25C. 9. Between any two switches. 2 -1 -10 -1 -10 0.1 0.1 6 1 10 1 10 V A A A A
Negative Supply Current, I-
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, rON
Full V+ = 5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (See Figure 5) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V, (Note 8) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V, (Note 8) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V, (Note 8) V+ = 5.5V, VCOM = VNO or VNC = 4.5V, (Note 8) +25 Full +25 Full +25 Full +25 Full +25 Full
0 -1 -10 -1 -10 -1 -5 -1 -10
125 0.002 0.002 0.002 0.002 -
V+ 225 280 1 10 1 10 1 5 1 10
V nA nA nA nA nA nA nA nA
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF), (ISL84051) COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) COM ON Leakage Current, ICOM(ON)
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 1) V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0V to 3V, (See Figure 1) V+ = 5.5V, VNO or VNC = 3V, RL = 300, CL = 35pF, VIN = 0V to 3V, (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 15pF, f = 100kHz, VNO or VNC = 1VRMS, (See Figures 4 and 6) +25 Full +25 Full +25 +25 +25 +25 90 60 30 2 <90 <-90 200 275 125 175 10 ns ns ns ns ns pC dB dB V+ = 5.5V, VINH, VADD = 0V or V+ Full Full Full 2.4 -1 0.03 0.8 1 V V A
Inhibit Turn-OFF Time, tOFF
Break-Before-Make Time, tBBM Charge Injection, Q OFF Isolation Crosstalk, (Note 9) (ISL84052, ISL840533 Only)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 5.5V, V- = 0V, VINH, VADD = 0V or V+, Switch On or Off Full +25 Full 2 -1 -10 12 1 10 V A A
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053
Electrical Specifications: 3.3V Supply
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, rON
Full V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V +25 Full
0 -1 -10 -1 -10 -1 -5 -1 -10
250 0.002 0.002 0.002 0.002 -
V+ 525 700 1 10 1 10 1 5 1 10
V nA nA nA nA nA nA nA nA
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM OFF Leakage Current, ICOM(OFF), (ISL84051) COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) COM ON Leakage Current, ICOM(ON)
V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V, (Note 8) V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V, (Note 8) V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V, (Note 8) V+ = 3.6V, VCOM = VNO or VNC = 3V, (Note 8)
+25 Full +25 Full +25 Full +25 Full
DIGITAL INPUT CHARACTERISTICS Input Voltage High, VINH, VADDH Input Voltage Low, VINL, VADDL Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 3V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 1) V+ = 3V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 1) V+ = 3.6V, VNO or VNC = 1.5V, RL = 300, CL = 35pF, VIN = 0 to 3V, (See Figure 3) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 15pF, f = 100kHz, VNO or VNC = 1VRMS, (See Figures 4 and 6) +25 Full +25 Full +25 +25 +25 +25 180 100 90 1 <90 <-90 600 700 300 400 10 ns ns ns ns ns pC dB dB V+ = 3.6V, VINH, VADD = 0V or V+ Full Full Full 2.4 -1 0.03 0.8 1 V V A
Inhibit Turn-OFF Time, tOFF
Break-Before-Make Time, tBBM Charge Injection, Q OFF Isolation Crosstalk, (Note 9) (ISL84052, ISL84053 Only)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 3.6V, V- = 0V, VINH, VADD = 0V or V+, Switch On or Off Full +25 Full 2 -1 -10 12 1 10 V A A
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms
C V+ C VC
V+
NO0 NO1-NO7 INH
ISL84051 COM VOUT
LOGIC INPUT
GND ADDA-C
RL 300
CL 35pF
C 3V LOGIC INPUT 50% 0V tON tr < 20ns tf < 20ns V+
V+
C
V-
C
NO0 NO1-NO3 INH
ISL84052 COM VOUT
90% SWITCH OUTPUT 0V tOFF
VOUT
90%
LOGIC INPUT
GND ADDA-B
RL 300
CL 35pF
Logic input waveform is inverted for switches that have the opposite logic sense.
V+ C
C
V-
C
V+
NCX NOX INH
ISL84053 COMX GND ADDX VOUT
LOGIC INPUT
RL 300
CL 35pF
Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) ----------------------R L + r ON FIGURE 1A. INHIBIT tON /tOFF MEASUREMENT POINTS FIGURE 1B. INHIBIT tON /tOFF TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms
(Continued)
C V+ C VC
V+ VC
NO0 NO7 NO1-NO6
ISL84051 COM VOUT
ADDA-C GND LOGIC INPUT
INH RL 300
CL 35pF
C 3V LOGIC INPUT 0V tTRANS VC VNOX SWITCH OUTPUT VOUT 50% tr < 20ns tf < 20ns V+
V+
C
V-
C
NO0 NO3 NO1-NO2
ISL84052 COM VOUT
90% LOGIC INPUT
ADDA-B GND
INH RL 300
CL 35pF
0V 10% VNOX
V+ tTRANS C
C
V-
C
Logic input waveform is inverted for switches that have the opposite logic sense.
V-
V+
NCX NOX
ISL84053 COMX INH RL 300 VOUT
C ADDX LOGIC INPUT GND
CL 35pF
Repeat test for other switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (NO or NC) R + r L ON FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES (Continued)
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms
(Continued)
V+ C VC
3V LOGIC INPUT OFF ON 0V 0 ADDX SWITCH OUTPUT VOUT Q = VOUT x CL VOUT VG GND INH LOGIC INPUT OFF RG NO or NC COM
VOUT
CL 1nF
FIGURE 2A. Q MEASUREMENT POINTS
Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION
V+ C
C
V-
C
V+
NO0-NO7 ADDA-C ISL84051
VOUT COM RL 300 CL 35pF
LOGIC INPUT GND INH
3V LOGIC INPUT 0V
tr < 20ns tf < 20ns
V+ C
C
V-
C
V+ SWITCH OUTPUT VOUT 0V tBBM 80% LOGIC INPUT
NO0-NO3 ADDA-B ISL84052 GND
VOUT COM RL 300 CL 35pF
INH
V+ C
C
V-
C
V+
NOX NCX ADDX
VOUT COMX ISL84053 RL 300 CL 35pF
LOGIC INPUT
GND
INH
Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms
V+ C
(Continued)
VV+ C V-
C
C
SIGNAL GENERATOR
NO or NC
rON = V1/1mA NO or NC VNX 0V or V+ ADDX 0V or V+
COM
1mA
V1
0V or V+ ADDX
ANALYZER RL
GND
INH
COM
GND
INH
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
V+
C
V-
C
V+
C
V-
C
SIGNAL GENERATOR
50 NOA or NCA COMA ISL84052 AND ISL84053 IMPEDANCE ANALYZER NOB or NCB NC
NO or NC
0V or V+ ADDX
ADDX 0V or V+
COM
ANALYZER RL
GND
COMB
INH
GND
INH
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Detailed Description
The ISL84051, ISL84052, ISL84053 analog switches offer precise switching capability from a bipolar 2V to 6V or a single 2V to 12V supply with low on-resistance (60) and high speed operation (tON = 50ns, tOFF = 40ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (3W), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection.
Power-Supply Considerations
The ISL8405X construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL8405X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (6V or 12V single supply), as well as room for overshoot and noise spikes. This family of switches performs equally well when operated with bipolar or single voltage supplies. The minimum recommended supply voltage is 2V or 2V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the Electrical Specification tables and "Typical Performance Curves TA = +25C, Unless Otherwise Specified" on page 13 for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V- (see Figure 8). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages.
OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS V+ 1k
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH level is about 3.5V. This is still below the CMOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past 100MHz (see Figure 17). Figure 17 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch's input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high off isolation and crosstalk rejection provided by this family. At 10MHz, off isolation is about 55dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
OPTIONAL PROTECTION DIODE
LOGIC VNO OR NC VCOM
VOPTIONAL PROTECTION DIODE
FIGURE 8. INPUT OVERVOLTAGE PROTECTION
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND.
Typical Performance Curves TA = +25C, Unless Otherwise Specified
70 60 50 40 30 rON () 20 400 V- = 0V 300 200 +85C 100 -40C 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 +25C V- = -5V VCOM = (V+) - 1V ICOM = 1mA +85C +25C -40C 225 200 175 150 125 100 75 160 140 120 100 80 60 100 90 +85C 80 70 +25C 60 50 40 1 0 +85C +25C -40C V+ = 2.7V V- = 0V ICOM = 1mA
rON ()
+85C +25C -40C V+ = 5V V- = 0V V+ = 3.3V V- = 0V
-40C 2 VCOM (V) 3 4 5
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
120 110 100 90 80 70 60 50 90 80 70 60 50 40 30 60 50 40 30 20 -5
ICOM = 1mA
+85C +25C -40C
VS = 2V
2
1
VS = 3V +85C +25C -40C VS = 5V Q (pC)
0 V+ = 5V V- = 0V -1 VS = 5V
rON ()
+25C
+85C
-2
-40C -4 -3 -2 -1 0 VCOM (V) 1 2 3 4 5
-3 -5 -2.5 0 VCOM (V) 2.5 5
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
500 400 300 200 100 tON (ns) 0 250 200 150 100 50 0 2 3 4 5 6 7 V+ (V) 8 9 10 11 12 -40C +85C +25C -40C V- = 0V V- = -5V -40C +25C +25C +85C tOFF (ns) 0 100 80 60 40 20 0 2 -40C 3 4 5 6 7 V+ (V) 8 9 10 11 12 VCOM = (V+) - 1V 200 -40C 150 100 +25C 50 -40C V- = 0V +85C +25C +85C +25C V- = -5V VCOM = (V+) - 1V
FIGURE 13. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 14. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE
300
VCOM = (V+) - 1V V- = 0V
250 VCOM = (V+) - 1V 200
250
tRANS (ns)
tRANS (ns)
200
150
150
100
+25C +85C
100 +25C +85C 50 -40C 0 2 3 4 5 6 7 8 9 10 11 12 13 V+ (V) 0 2 3 4 V (V) 5 6 50 -40C
FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE
FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE
NORMALIZED GAIN (dB)
VS = 5V 3 GAIN 0
-10 VIN = 0.2VP-P to 5VP-P ISL84053 ISL84051 ISL84052 CROSSTALK (dB) V+ = 3V to 12V or -20 VS = 2V to 5V RL = 50 -30 -40 -50 -60 ISOLATION -70 -80 CROSSTALK -90 -100 -110 1k
10 20 30 OFF ISOLATION (dB) 40 50 60 70 80 90 100 110 100M 500M
-3
ISL84053 PHASE ISL84051 ISL84052
45 90 135 180
RL = 50 1M 10M 100M 600M FREQUENCY (Hz)
PHASE (DEGREES)
0
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 17. FREQUENCY RESPONSE
FIGURE 18. CROSSTALK AND OFF ISOLATION
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): VTRANSISTOR COUNT: ISL84051: 193 ISL84052: 193 ISL84053: 193 PROCESS: Si Gate CMOS
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FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 16 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 16 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
16
FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D E1
A2 c 0.10(0.004) C AM BS
MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 6.25 0.50 16 8o 0o 8o MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 6.50 0.70 NOTES 9 3 4 6 7 Rev. 1 2/02
MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 0.246 0.020 16 0o
MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 0.256 0.028
A1
e
b 0.10(0.004) M
e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
17
FN6047.7 March 15, 2007
ISL84051, ISL84052, ISL84053 Shrink Small Outline Plastic Packages (SSOP) Quarter Size Outline Plastic Packages (QSOP)
N INDEX AREA E -B1 2 3 0.25 0.010 h x 45 L GAUGE PLANE H 0.25(0.010) M BM
M16.15A
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE (0.150" WIDE BODY) INCHES SYMBOL A A1
SEATING PLANE -AD -CA
MILLIMETERS MIN 1.55 0.102 1.40 0.20 0.191 4.80 3.81 MAX 1.73 0.249 1.55 0.31 0.249 4.98 3.99 NOTES 9 3 4 5 6 7 8 Rev. 2 6/04
MIN 0.061 0.004 0.055 0.008 0.0075 0.189 0.150
MAX 0.068 0.0098 0.061 0.012 0.0098 0.196 0.157
A2 B C D
A1 0.10(0.004) A2 C
E e H h L
e
B 0.17(0.007) M C AM BS
0.025 BSC 0.230 0.010 0.016 16 0 8 0.244 0.016 0.035
0.635 BSC 5.84 0.25 0.41 16 0 6.20 0.41 0.89
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of "B" dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
N
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6047.7 March 15, 2007

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